View AD9410BSQ_940726.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9410 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000 10-bit, 210 msps a/d converter functional block diagram t/h a in a in ds encode ds encode adc 10-bit core timing and synchronization port a dfs i/p ref in ref out reference v dd dgnd v d agnd v cc or a d9 a ?0 a dco or b d9 b ?0 b 10 dco ad9410 10 port b 10 features snr = 54 db with 99 mhz analog input 500 mhz analog bandwidth on-chip reference and track/hold 1.5 v p-p differential analog input range 5.0 v and 3.3 v supply operation 3.3 v cmos/ttl outputs power: 2.1 w typical at 210 msps demultiplexed outputs each at 105 msps output data format option data sync input and data clock output provided interleaved or parallel data output option applications communications and radar local multipoint distribution service (lmds) high-end imaging systems and projectors cable reverse path point-to-point radio link general description the ad9410 is a 10-bit monolithic sampling analog-to-digital converter with an on-chip track-and-hold circuit and is opti- mized for high-speed conversion and ease of use. the product operates at a 210 msps conversion rate, with outstanding dynamic performance over its full operating range. the adc requires a 5.0 v and 3.3 v power supply and up to a 210 mhz differential clock input for full performance operation. no external reference or driver components are required for many applications. the digital outputs are ttl/cmos-compatible, and separate output power supply pins also support interfacing with 3.3 v logic. the clock input is differential and ttl/cmos-compatible. the 10-bit digital outputs can be operated from 3.3 v (2.5 v to 3.6 v) supplies. two output buses support demultiplexed data up to 105 msps rates, and binary or two? complement output coding format is available. a data sync function is provided for tim ing- dependent applications. an output clock simplifies interfacing to external logic. the output data bus timing is selectable for parallel or interleaved mode, allowing for flexibility in latching out put data. fabricated on an advanced bicmos process, the ad9410 is available in an 80-lead surface-mount plastic package (powerquad 2) specified over the industrial temperature range (?0 c to +85 c). powerquad is a registered trademark of amkor electronics, inc. product highlights high resolution at high speed?he architecture is specifically designed to support conversion up to 210 msps with outstand- ing dynamic performance. demultiplexed output?utput data is decimated by two and provided on two data ports for ease of data transport. output data clock?he ad9410 provides an output data clock synchronous with the output data, simplifying the timing between data and other logic. data sync hronization? ds input is provided to allow for synchronization of two or more ad9410s in a system, or to synchronize data to a specific output port in a single ad9410 system.
rev. 0 C2C ad9410?pecifications dc specifications test parameter temp level min typ max unit resolution 10 bits dc accuracy no missing codes 1 full iv guaranteed differential nonlinearity 25 c i ?.0 0.5 +1.25 lsb full vi ?.0 +1.5 lsb integral nonlinearity 25 c i ?.5 1.65 +2.5 lsb full vi ?.0 +3.0 lsb gain error 25 c i ?.0 0 +6.0 % fs gain tempco full v 130 ppm/ c analog input input voltage range (with respect to a in ) full v 768 mv p-p common-mode voltage full v 3.0 v input offset voltage 25 c i ?5 +3 +15 mv full vi ?0 +20 mv reference voltage full vi 2.4 2.5 2.6 v reference tempco full v 50 ppm/ c input resistance full vi 610 875 1250 ? input capacitance 25 cv 3 pf analog bandwidth, full power 25 c v 500 mhz power supply power dissipation ac 2 25 c v 2.1 w power dissipation dc 3 full vi 2.0 2.4 w i vcc 3 full vi 128 145 ma i vd 3 full vi 401 480 ma power supply rejection ratio psrr 25 c i ?.5 +0.5 +7.5 mv/v notes 1 package heat slug should be attached when operating at greater than 70 c ambient temperature. 2 encode = 210 msps, a in = ?.5 dbfs 10 mhz sine wave, i vdd = 31 ma typical at c load = 5 pf. 3 encode = 210 msps, a in = dc, outputs not switching. specifications subject to change without notice. switching specifications test parameter temp level min typ max unit switching performance maximum conversion rate full vi 210 msps minimum conversion rate full iv 100 msps encode pulsewidth high (t eh )25 c iv 1.2 2.4 ns encode pulsewidth low (t el )25 c iv 1.2 2.4 ns aperture delay (t a )25 c v 1.0 ns aperture uncertainty (jitter) 25 c v 0.65 ps rms output valid time (t v ) full vi 3.0 ns output propagation delay (t pd ) full vi 7.4 ns output rise time (t r )25 c v 1.8 ns output fall time (t f )25 c v 1.4 ns clkout propagation delay 1 (t cpd ) full vi 2.6 4.8 6.4 ns data to dco skew (t pd ? cpd ) full iv 0 1 2 ns ds setup time (t sds ) full iv 0.5 ns ds hold time (t hds ) full iv 0 ns interleaved mode (a, b latency) full vi a = 6, b = 6 cycles parallel mode (a, b latency) full vi a = 7, b = 6 cycles notes 1 c load = 5 pf. specifications subject to change without notice. (v dd = 3.3 v, v d = 3.3 v, v cc = 5.0 v; 2.5 v external reference; a in = ?.5 dbfs; clock input = 210 msps; t a = 25 c; unless otherwise noted.) (v dd = 3.3 v, v d = 3.3 v, v cc = 5.0 v; 2.5 v external reference; a in = ?.5 dbfs; clock input = 210 msps; t a = 25 c; unless otherwise noted.)
rev. 0 C3C ad9410 digital specifications test parameter temp level min typ max unit digital inputs dfs, input logic ??voltage full iv 4 v dfs, input logic ??voltage full iv 1 v dfs, input logic ??current full v 50 a dfs, input logic ??current full v 50 a i/p input logic ??current 1 full v 400 a i/p input logic ??current 1 full v 1 a encode, encode differential input voltage full iv 0.4 v encode, encode differential input resistance full v 1.6 k ? encode, encode common-mode input voltage 2 full v 1.5 v ds, ds differential input voltage full iv 0.4 v ds, ds common-mode input voltage full v 1.5 v digital input pin capacitance 25 cv 3 pf digital outputs logic ??voltage (v dd = 3.3 v) full vi v dd ?0.05 v logic ??voltage (v dd = 3.3 v) full vi 0.05 v output coding binary or two? complement notes 1 i/p pin logic ??= 5 v, logic ??= gnd. it is recommended to place a series 2.5 k ? ( 10%) resistor to v dd when setting to logic ??to limit input current. 2 see encode input section in applications section. specifications subject to change without notice. ac specifications test parameter temp level min typ max unit dynamic performance transient response 25 cv 2 ns overvoltage recovery time 25 cv 2 ns signal-to-noise ratio (snr) (without harmonics) f in = 10.3 mhz 25 c i 52.5 55 db f in = 82 mhz 25 c i 52 54 db f in = 160 mhz 25 cv 53 db signal-to-noise ratio (sinad) (with harmonics) f in = 10.3 mhz 25 c i 51 54 db f in = 82 mhz 25 c i 50 53 db f in = 160 mhz 25 cv 52 db effective number of bits f in = 10.3 mhz 25 c i 8.3 8.8 bits f in = 82 mhz 25 c i 8.1 8.6 bits f in = 160 mhz 25 c v 8.4 bits second harmonic distortion f in = 10.3 mhz 25 c i ?6 ?5 dbc f in = 82 mhz 25 c i ?5 ?3 dbc f in = 160 mhz 25 c v ?5 dbc third harmonic distortion f in = 10.3 mhz 25 c i ?8 ?9 dbc f in = 82 mhz 25 c i ?7 ?7 dbc f in = 160 mhz 25 c v ?2 dbc spurious free dynamic range (sfdr) f in = 10.3 mhz 25 c i 56 61 dbc f in = 82 mhz 25 c i 54 60 dbc f in = 160 mhz 25 c v 58 dbc two-tone intermod distortion imd 1 f in1 = 80.3 mhz, f in2 = 81.3 mhz 25 c v 58 dbfs notes 1 in1, in2 level = ? dbfs. specifications subject to change without notice. (v dd = 3.3 v, v d = 3.3 v, v cc = 5.0 v; 2.5 v external reference; a in = ?.5 dbfs; clock input = 210 msps; t a = 25 c; unless otherwise noted.) (v dd = 3.3 v, v d = 3.3 v, v cc = 5.0 v; 2.5 v external reference; a in = ?.5 dbfs; clock input = 210 msps; t a = 25 c; unless otherwise noted.)
rev. 0 ad9410 C4C ain encode encode ds ds port a d7 d0 port b d7 d0 port a d7 d0 port b d7 d0 dco dco sample n 1 sample n sample n+4 sample n+5 sample n+3 t el t eh 1/f s t a t sds t hds sample n 2 sample n+1 sample n+2 sample n+6 interleaved data out invalid t v t pd static invalid invalid invalid invalid invalid data n data n+2 data n+3 data n+1 static parallel data out t cpd data n+1 data n data n+2 invalid invalid invalid invalid invalid invalid invalid static static static figure 1. timing diagram
rev. 0 ad9410 C5C ordering guide temperature package package model range description option AD9410BSQ 40 c to +85 c powerquad 2 sq-80 ad9410/pcb 25 c evaluation board caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9410 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device explanation of test levels test level i. 100% production tested. ii. 100% production tested at 25 c and sample tested at specified temperatures. iii. sample tested only. iv. parameter is guaranteed by design and characterization testing. v. parameter is a typical value only. vi. 100% production tested at 25 c; guaranteed by design and characterization testing for industrial temperature range. absolute maximum ratings 1 v d , v cc, v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 v analog inputs . . . . . . . . . . . . . . . . . . . . . 0 v to v cc + 0.5 v digital inputs . . . . . . . . . . . . . . . . . . . . . 0 v to v dd + 0.5 v vref in . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to v d + 0.5 v digital output current . . . . . . . . . . . . . . . . . . . . . . . . 20 ma operating temperature . . . . . . . . . . . . . . . . ?5 c to +125 c storage temperature . . . . . . . . . . . . . . . . . . ?5 c to +150 c maximum junction temperature 2 . . . . . . . . . . . . . . . . 150 c notes 1 absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability is not necessarily implied. exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. 2 typical ja = 22 c/w (heat slug not soldered), typical ja = 16 c/w (heat slug soldered), for multilayer board in still air with solid ground plane.
rev. 0 ad9410 C6C pin function descriptions pin no. mnemonic function 1, 2, 8, 9, 12, 13, 16, 17, 20, 21, 24, agnd analog ground. 27, 28, 29, 30, 71, 72, 73, 74, 77, 78 3, 7, 14, 15 v cc 5 v supply. (regulate to within 5%.) 4 ref out internal reference output. 5 ref in internal reference input. 6 dnc do not connect. 10 a in analog input?rue. 11 a in analog input?omplement. 18 encode clock input?rue. 19 encode clock input?omplement. 22 ds data sync (input)?rue. tie low if not used. 23 ds data sync (input)?omplement. float and decouple with 0.1 f capacitor if not used. 25, 26, 31, 32, 69, 70, 75, 76 v d 3.3 v analog supply. (regulate to within 5%.) 33, 40, 49, 52, 59, 68 dgnd digital ground. 34, 41, 48, 53, 60, 67 v dd 3.3 v digital output supply. (2.5 v to 3.6 v) 35?9 d b0 ? b4 digital data output for channel b. (lsb = d b0 .) 42?6 d b5 ? b9 digital data output for channel b. (msb = d b9 .) 47 or b data overrange for channel b. 50 dco clock output?omplement. 51 dco clock output?rue. 54?8 d a0 ? a4 digital data output for channel a. (lsb = d a0 .) 61?5 d a5 ? a9 digital data output for channel a. (msb = d a9 .) 66 or a data overrange for channel a. 79 dfs data format select. high = two? complement, low = binary. 80 i/p interleaved or parallel output mode. low = parallel mode, high = interleaved mode. if tying high, use a current limiting series resistor (2.5 k ? ) to the 5 v supply.
rev. 0 ad9410 C7C pin configuration pin 1 identifier top view 80-lead powerquad2 (not to scale) ad9410 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 agnd agnd v cc ref out ref in dnc v cc agnd agnd a in a in agnd agnd v cc v cc agnd agnd encode encode agnd agnd ds ds agnd v d v d agnd agnd agnd agnd v d v d dgnd v dd (lsb) d b0 d b1 d b2 d b3 d b4 dgnd v dd d b5 d b6 d b7 d b8 d b9 (msb) or b v dd dgnd dco dco dgnd v dd d a0 (lsb) d a1 d a2 d a3 d a4 dgnd v dd d a5 d a6 d a7 d a8 d a9 (msb) or a v dd dgnd v d v d agnd agnd agnd agnd v d v d agnd agnd dfs i/p dnc do not connect
rev. 0 ad9410 C8C definitions of specifications analog bandwidth the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db. aperture delay the delay between the 50% point of the rising edge of the encode command and the instant at which the analog input is sam pled. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. differential analog input resistance, differential analog input capacitance, and differential analog input impedance the real and complex impedances measured at each analog input port. the resistance is measured statically and the capaci- tance and differential input impedances are measured with a network analyzer. differential analog input voltage range the peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. peak differential voltage is computed by observing the voltage on a single pin and subtract- ing the voltage from the other pin, which is 180 degrees out of phase. peak-to-peak differential is computed by rotat ing the inputs phase 180 degrees and taking the peak measurement again. the difference is then computed between both peak measurements. differential nonlinearity the deviation of any code width from an ideal 1 lsb step. effective number of bits the effective number of bits (enob) is calculated from the measured sinad based on the equation. enob sinad db full scale amplitude input amplitude measured = + ? ? ? ? ? ? . log . 176 20 602 encode pulsewidth/duty cycle pulsewidth high is the minimum amount of time that the encode p ulse should be left in logic 1 state to achieve rated performance; pulsewidth low is the minimum time encode pulse should be left in low state. see timing implica- tions of changing t ench in text. at a given clock rate, these specs define an acceptable encode duty cycle. full-scale input power expressed in dbm. computed using the following equation: power v z full scale full scale input rms = ? ? ? ? ? ? ? ? ? ? ? ? ? ? 10 0 001 2 log . harmonic distortion, second the ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dbc. harmonic distortion, third the ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dbc. integral nonlinearity the deviation of the transfer function from a reference line measured in fractions of 1 lsb using a best straight line determined by a least-square curve fit. minimum conversion rate the encode rate at which the snr of the lowest analog signal frequency drops by no more than 3 db below the guaranteed limit. maximum conversion rate the encode rate at which parametric testing is performed. output propagation delay the delay between a differential crossing of encode and encode and the time when all output data bits are within valid logic levels. out-of-range recovery time out-of-range recovery time is the time it takes for the adc to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. noise (for any range within the adc) vz noise fs signal dbm dbfs = ? ? ? ? ? ? ? || . 0 001 10 10 where z is the input impedance, fs is the full scale of the d evice for the frequency in question, snr is the value for the particular input level, and signal is the signal level within the adc reported in db below full scale. this value includes both thermal and quantization noise. power supply rejection ratio the ratio of a change in input offset voltage to a change in power supply voltage. signal-to-noise-and-distortion (sinad) the ratio of the rms signal amplitude (set 0.5 db below full scale) to the rms value of the sum of all other spectral compo- nents, including harmonics, but excluding dc. signal-to-noise ratio (without harmonics) the ratio of the rms signal amplitude (set at 0.5 db below full scale) to the rms value of the sum of all other spectral compo- nents, excluding the first five harmonics and dc. spurious-free dynamic range (sfdr) the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. the peak spurious compo- nent may or may not be a harmonic. may be reported in dbc (i.e., degrades as signal level is lowered), or dbfs (always related back to converter full scale). transient response time transient response time is defined as the time it takes for the adc to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale. two-tone intermodulation distortion rejection the ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dbc. two-tone sfdr the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. may be reported in dbc (i.e., degrades as signal level is lowered), or in dbfs (always related back to converter full scale). worst other spur the ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic) reported in dbc.
rev. 0 ad9410 C9C v cc 1.5k a in 2.25k 1.5k 2.25k a in figure 2. equivalent analog input circuit v cc vrefin figure 3. equivalent reference input circuit 17k v cc 17k 8k 8k encode 100 100 encode 450 450 figure 4 equivalent encode input circuit v dd digital output figure 5. equivalent digital output circuit table i. output coding (v ref = 2.5 v) digital outputs digital outputs step a in a in offset binary two? complement or a , or b > 0.768 11 1111 1111 01 1111 1111 1 1023 0.768 11 1111 1111 01 1111 1111 0 ?? ? ? ? ?? ? ? ? 513 0.0015 10 0000 0001 00 0000 0001 0 512 0.0 10 0000 0000 00 0000 0000 0 511 0.0015 01 1111 1111 11 1111 1111 0 ?? ? ? ? ?? ? ? ? 0 0.768 00 0000 0000 10 0000 0000 0 < 0.768 00 0000 0000 10 0000 0000 1 v cc vrefout figure 6. equivalent reference output circuit 100k dfs v cc figure 7. equivalent dfs input circuit 7.5k ds 300 17.5k 300 ds v cc figure 8. equivalent ds input circuit 7.5k i/p 300 17.5k v cc figure 9. equivalent i/p input circuit
rev. 0 ad9410 C10C mhz 0 0 db 20 40 60 80 100 120 105 encode = 210msps a in = 40mhz @ 0.5dbfs snr = 54.5db sinad = 53.5db tpc 1. single tone at 40 mhz, encode = 210 msps mhz 0 0 db 20 40 60 80 100 120 105 encode = 210msps a in = 100mhz @ 0.5dbfs snr = 53.5db sinad = 52.5db tpc 2. single tone at 100 mhz, encode = 210 msps mhz 0 0 db 20 40 60 80 100 120 105 encode = 210msps a in = 160mhz @ 0.5dbfs snr = 53db sinad = 52db tpc 3. single tone at 160 mhz, encode = 210 msps typical performance characteristics a in mhz 51 0 db 50 49 48 47 46 45 50 100 150 200 250 53 55 snr sinad 52 54 tpc 4. snr/sinad vs. a in encode = 210 msps mhz 53.0 100 db 52.5 52.0 51.5 51.0 50.5 50.0 120 140 160 200 240 54.0 55.0 snr sinad 53.5 54.5 180 220 tpc 5. snr/sinad vs. f s a in = 70 mhz ns 40 0 db 35 30 0.5 1.0 1.5 2.5 4.0 55 60 50 2.0 3.5 45 3.0 sinad snr tpc 6. snr/sinad vs. encode positive pulsewidth (f s = 210 msps, a in = 70 mhz)
rev. 0 ad9410 C11C mhz 0 0 db 20 40 60 80 100 120 105 encode = 210msps a in 1, a in 2 = 7dbfs sfdr = 62dbfs tpc 7. two tone test a in 1 = 80.3 mhz, a in 2 = 81.3 mhz temperature c 54.5 40 db 54.0 53.5 53.0 52.5 52.0 51.5 20 0 20 40 60 80 100 120 55.0 55.5 snr sinad tpc 8. snr/sinad vs. temperature, encode = 210 msps, a in = 70 mhz temperature c 70 40 db 68 66 64 62 60 58 20 0 20 40 60 80 100 120 72 74 h2 h3 tpc 9. second and third harmonics vs. temperature; a in = 70 mhz, encode = 210 msps analog supply 2.48 4.0 volts 2.47 2.46 4.2 4.4 4.6 5.0 5.6 2.51 2.52 2.50 4.8 5.4 2.49 5.2 (3/' & 0:( )1 msps 110 100 ma 60 10 120 140 160 200 260 310 210 180 160 220 360 410 460 iahi3 iahi5 ivdd tpc 11. power supply currents vs. encode ma 2.35 0 volts 2.30 2.25 0.5 1.0 2.0 1.5 2.40 2.5 2.45 2.50 2.55 tpc 12. vref out vs. i load
rev. 0 ad9410 C12C temperature c 40 volts 20 0 40 20 60 2.503 2.502 2.501 2.500 2.499 2.498 2.497 2.496 80 tpc 13. vref out vs. temperature temperature c 40 ns 20 0 40 20 60 5.1 4.9 4.7 4.5 4.3 4.1 3.9 80 t pd t v t cpd tpc 14. t pd , t v , t cpd vs. temperature
rev. 0 ad9410 C13C application notes theory of operation the ad9410 architecture is optimized for high speed and ease of use. the analog inputs drive an integrated high bandwidth track-and-hold circuit that samples the signal prior to quantiza- tion by the flash 10-bit core. for ease of use the part includes an onboard reference and input logic that accepts ttl, cmos, or pecl levels. using the ad9410 encode input any high-speed a/d converter is extremely sensi tive to the quality of the sampling clock provided by the user. a track/hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock will be combined with the desired signal at the a/d output. for that reason, considerable care has been taken in the design of the encode input of the ad9410, and the user is advised to give commensurate thought to the clock source. to limit snr degradation to less than 1 db, a clock source with less than 1.25 ps rms jitter is required for sampling at nyquist. (valpey fisher vf561 is an example.) note that required jitter accuracy is a function of input frequency and amplitude. consult analog devices application note an-501, aperture uncer- tainty and adc system performance, for more information. the encode input is fully ttl/cmos-compatible. the clock input can be driven differentially or with a single-ended signal. best performance will be obtained when driving the clock differentially. both encode inputs are self-biased to 1/3 v cc by a high impedance resistor divider. (see equivalent circuits section.) single-ended clocking, which may be appropriate for lower frequency or nondemanding applications, is accomplished by driving the encode input directly and placing a 0.1 f capacitor at encode . 0.1 f encode encode ad9410 ttl/cmos gate figure 10. driving single-ended encode input at ttl/cmos levels an example where the clock is obtained from a pecl driver is shown in figure 11. note t hat the pecl driver is ac-coupled to the encode inputs to minimize input c urrent loading. the ad9410 can be dc-coupled to pecl logic levels resulting in the encode input currents increasing to approximately 8 ma typically. this is due to the difference in dc bias between the encode inputs and a pecl driver. (see equivalent cir- cuits section.) pecl gate gnd 510 510 0.1 f 0.1 f encode encode ad9410 figure 11. driving the encode inputs differentially analog input the analog input to the ad9410 is a differential buffer. for best dynamic performance, impedances at a in and a in should match. the analog input has been optimized to provide superior wideband performance and requires that the analog inputs be driven differentially. snr and sinad performance will degrade significantly if the analog input is driven with a single-ended signal. a wideband transformer such as minicircuits adt1-1wt can be used to provide the differential analog inputs for applica- tions that require a single-ended-to-differential conversion. both analog inputs are self-biased by an on-chip resistor divider to a nominal 3 v. (see equivalent circuits section.) special care was taken in the design of the analog input section of the ad9410 to prevent damage and corruption of data when the input is overdriven. the nominal input range is 1.5 v diff p-p. the nominal differential input range is 768 mv p-p 2. 2.616 volts 3.384 3.000 a in a in figure 12. typical analog input levels digital outputs the digital outputs are ttl/cmos-compatible for lower power consumption. the outputs are biased from a separate supply (v dd ), allowing easy interface to external logic. the outputs are cmos devices which will swing from ground to v dd (with no dc load). it is recommended to minimize the capacitive load the adc drives by keeping the output traces short (<1 inch, for a total c load < 5 pf). it is also recommended to place low value (20 ? ) series damping resistors on the data lines to reduce switch- ing transient effects on performance. clock outputs (dco, dco ) the input encode is divided by two and available off-chip at dco and dco . these clocks can facilitate latching off-chip, providing a low skew clocking solution (see timing diagram). these clocks can also be used in multiple ad9410 systems to synchronize the adcs. depending on application, dco or dco can be buffered and used to drive the ds inputs on a second ad9410, ensuring synchronization. the on-chip clock buffers should not drive more than 5 pf 7 pf of capacitance to limit switching transient effects on performance. voltage reference a stable and accurate 2.5 v voltage reference is built into the ad9410 (vref out). the input range can be adjusted by varying the reference voltage. no appreciable degradation in perform ance occurs when the reference is adjusted 5%. the full- scale range of the adc tracks reference voltage changes linearly within the 5% tolerance.
rev. 0 ad9410 C14C timing the ad9410 provides latched data outputs, with six pipeline delays in interleaved mode (see figure 1). in parallel mode, the a port has one additional cycle of latency added on-chip to line up transitions at the data ports resulting in a latency of seven cycles for the a port. the length of the output data lines and loads placed on them should be minimized to reduce transients within the ad9410; these transients can detract from the converter s dynamic performance. the minimum guaranteed conversion rate of the ad9410 is 100 msps. at internal clock rates below 100 msps, dynamic performance may degrade. note that lower effective sampling rates can be obtained simply by sampling just one output port decimating the output by two. lower sampling frequencies can also be accommodated by restricting the duty cycle of the clock such that the clock high pulsewidth is a maximum of 5 ns. evaluation board the ad9410 evaluation board offers an easy way to test the ad9410. the board requires an analog input, clock, and 3 v, 5 v power supplies. the digital outputs and output clocks are available at a standard 80-lead header p2, p3. the board has several different modes of operation, and is shipped in the fol- lowing configuration: output timing = parallel mode output format = offset binary internal voltage reference power connector power is supplied to the board via detachable 4-pin power strips p1, p4, p5. vdac optional dac supply input (3.3 v) ext ref optional external vref input (2.5 v) v dd logic supply (3.3 v) 3.3 va analog supply (3.3 v) 5 v analog supply (5 v) analog inputs the evaluation board accepts a 1.5 v p-p analog input signal centered at ground at smb j8. this input is terminated to 50 ? on the board at the transformer secondary, but can be termi- nated at the smb if an alternative termination is desired. the input is ac-coupled prior to the transformer. the transformer is band limited to frequencies between approximately 1 mhz and 400 mhz. encode the encode input to the board is at smb connector j1. the input is terminated on the board with 50 ? to ground. the (>0.5 v p-p) input is ac-coupled and drives a high-speed differential line receiver (mc10el16). this receiver provides sub- nan osecond rise times at its outputs a requirement for the adc clock inputs for optimum performance. the el16 outputs are pecl levels and are ac-coupled to meet the common- mode dc levels at the ad9410 encode inputs. reference the ad9410 has an on-chip reference of 2.5 v available at ref out (pin 4). most applications will simply tie this output to the ref in input (pin 5). this is accomplished by placing a jumper at e1, e6. an external reference can be used placing a jumper at e1, e3. output timing the chip has two timing modes (see timing diagram). inter- leaved mode is selected by jumper e11, e7. parallel mode is selected by jumper e11, e14. data format select data format select sets the output data format that the adc outputs. setting dfs (pin 79) low at e12, e10 sets the output format to be offset binary; setting dfs high at e12, e16 sets the output to be two s complement. ds pin the ds, ds inputs are available at smb connectors j9x and j10x. the board is shipped with ds pulled to ground by r26. ds is floating (r25x is not placed). dac outputs each channel is reconstructed by an on-board dual channel dac, an ad9751 to assist in debug. the performance of the dac has not been optimized and will not give an accurate measure of the full performance of the adc. it is a current output dac with on-board 50 ? termination resistors. the outputs are available at j3 and j4. data sync (ds) the data sync input, ds, can be used in applications req uir- ing that a given sample will appear at a specific output port a or b. when ds is held high, the adc data outputs and clock do not switch and are held static . synchronization is accomplished by the assertion (falling edge) of ds, within the timing constraints t sds and t hds relative to an encode rising edge. (on initial synchronization t hds is not relevant.) if ds falls within the required setup time (t sds ) before a given encode rising edge n, the analog value at that point in time will be digitized and avail- able at port b six cycles later (interleaved mode). the very next sample, n+1, will be sampled by the next rising encode edge and available at port a six cycles after that encode edge (interleaved mode). in dual parallel mode the a port has a seven cycle latency, the b port has a six cycle latency, but data is available at the same time.
rev. 0 ad9410 C15C daor da7 da8 da5 gnd 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 gnd da6 da9 c14 0.1 f gnd 3.3va gnd c11 0.1 f 3.3va 3.3va c10 0.1 f gnd 3.3va gnd r3 100 gnd e14 5v r24 100 r7 100 gnd e12 e16 5v r4 2.5k e10 gnd r6 100 vdd e11 e7 dbor gnd dcoc dcot gnd db9 db6 db7 da0 da1 da2 da3 da4 gnd vdd db8 vdd vdd c21 0.1 f gnd 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 v dd d b5 d b6 d b7 d b8 d b9 or b v dd dgnd dco dco dgnd v dd d a0 d a1 d a2 d a3 d a4 dgnd v dd c12 0.1 f gnd c22 0.1 f gnd vdd c18 0.1 f db5 gnd gnd db0 db1 db2 db4 gnd gnd 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 vdd c19 0.1 f 3.3va 3.3va gnd c15 0.1 f gnd 3.3va c16 0.1 f gnd 3.3va gnd r25x 50 gnd r26 50 j9x j10x agnd ds ds agnd v d v d agnd agnd agnd agnd v d v d dgnd v dd d b0 d b1 d b2 d b3 d b4 dgnd gnd 5v gnd gnd enct encc gnd gnd gnd c27 0.1 f e3 ext ref e6 5v c26 0.1 f gnd e1 r27 50 1 t1 1 : 1 gnd j8 ain c7 0.1 f gnd 2 3 6 5 4 c25 0.1 f gnd r23 50 gnd gnd gnd c24 0.1 f gnd 5v gnd ad9410 u3 gnd 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 c28 0.1 f 1 2 3 4 5 6 7 8 nc d d vbb vcc q q vee u1 r14 8.2k r9 24k 5v r19 8.2k r18 24k c6 0.1 f r8 50 gnd gnd j1 5v gnd c40 0.1 f gnd r15 330 gnd r11 330 enct encc c7 0.1 f c8 0.1 f gnd mc10el16 gnd gnd 5v p1 p5 p4 gnd vdd/3.3v gnd gnd 3.3va gnd 5v gnd vdac gnd ext ref gnd 1 2 3 4 1 2 3 4 1 2 3 4 gnd c4 10 f 5v 3.3va vdd ext ref vdac c5 10 f c3 10 f c2 10 f c1 10 f d a5 d a6 d a7 d a8 d a9 or a v dd dgnd v d v d agnd agnd agnd agnd v d v d agnd agnd dfs i/p agnd agnd v cc ref out ref in dnc v cc agnd agnd a in a in agnd agnd v cc v cc agnd agnd encode encode agnd note: r3, r6, r7, r24 optional (can be zero ) db3 figure 13a. pcb schematic
rev. 0 ad9410 C16C 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 p3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 gnd drb gnd dn9 dn8 dn7 dn6 dn5 dn4 dn3 dn1 dn2 dn0 gnd gnd gnd gnd gnd gnd gnd gnd header 40 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 gnd p2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 gnd dra gnd dm9 dm8 dm7 dm6 dm5 dm4 dm3 dm1 dm2 dm0 gnd gnd gnd gnd gnd gnd gnd header 40 8 7 6 5 4 3 2 1 r38 9 10 11 12 13 14 15 16 dn7 dn6 dn5 dn4 dn3 dn2 dn1 dn0 d7b d6b d5b d4b d3b d2b d1b d0b 1a 2a 3a 4a 5a 6a 7a 8a 1b 2b 3b 4b 5b 6b 7b 8b rpack 8 7 6 5 4 3 2 1 r28 9 10 11 12 13 14 15 16 nc nc nc nc nc dn9 dn8 1a 2a 3a 4a 5a 6a 7a 8a 1b 2b 3b 4b 5b 6b 7b 8b rpack nc nc nc nc nc d9b d8b 8 7 6 5 4 3 2 1 r36 9 10 11 12 13 14 15 16 dm2 dm1 dm0 nc nc nc nc 1a 2a 3a 4a 5a 6a 7a 8a 1b 2b 3b 4b 5b 6b 7b 8b rpack d2a d1a d0a nc nc nc nc nc nc 8 7 6 5 4 3 2 1 r34 9 10 11 12 13 14 15 16 dm9 dm8 dm7 dm6 dm5 dm4 dm3 d9a d8a d7a d6a d5a d4a d3a 1a 2a 3a 4a 5a 6a 7a 8a 1b 2b 3b 4b 5b 6b 7b 8b rpack 12 11 10 9 8 7 6 5 4 3 2 1 u5 13 14 15 16 17 18 19 20 21 22 23 24 d9b d8b d7b d6b d5b d4b d3b d2b d1b clkb d0b gnd dy9 dy8 dy7 dy6 dy5 dy4 dy3 dy2 dy1 gnd dy0 vcc y0 y1 y2 y3 y4 y5 y6 y7 y8 clk y9 de x0 x1 x2 x3 x4 x5 x6 x7 x8 gnd x9 c39 0.1 f 74lcxb21 gnd vdd 12 11 10 9 8 7 6 5 4 3 2 1 u4 13 14 15 16 17 18 19 20 21 22 23 24 vdd d9a d8a d7a d6a d5a d4a d3a d2a d1a clka d0a vcc y0 y1 y2 y3 y4 y5 y6 y7 y8 clk y9 de x0 x1 x2 x3 x4 x5 x6 x7 x8 gnd x9 c37 0.1 f 74lcxb21 gnd gnd dx9 dx8 dx7 dx6 dx5 dx4 dx3 dx2 dx1 gnd dx0 8 7 6 5 4 3 2 1 r39 9 10 11 12 13 14 15 16 dy7 dy6 dy5 dy4 dy3 dy2 dy1 dy0 db7 db6 db5 db4 db3 db2 db1 db0 1a 2a 3a 4a 5a 6a 7a 8a 1b 2b 3b 4b 5b 6b 7b 8b rpack 8 7 6 5 4 3 2 1 r29 9 10 11 12 13 14 15 16 dyor dy9 dy8 dbor db9 db8 1a 2a 3a 4a 5a 6a 7a 8a 1b 2b 3b 4b 5b 6b 7b 8b rpack 8 7 6 5 4 3 2 1 r40 9 10 11 12 13 14 15 16 dx2 dx1 dx0 da2 da1 da0 1a 2a 3a 4a 5a 6a 7a 8a 1b 2b 3b 4b 5b 6b 7b 8b rpack 8 7 6 5 4 3 2 1 r32 9 10 11 12 13 14 15 16 dxor dx9 dx8 dx7 dx6 dx4 dx3 1a 2a 3a 4a 5a 6a 7a 8a 1b 2b 3b 4b 5b 6b 7b 8b rpack daor da9 da8 da7 da6 da4 da3 da5 dx5 dra r44 00 3 u9 74ac86 1 2 dcota xora vdd e24 gnd e18 e17 r2 100 xora vdd e26 gnd e28 e27 r37 100 xorb clka 6 u9 74ac86 4 5 dcota xorb vdd e23 gnd e22 e25 r43 100 xord clkb 8 u9 9 10 dcota xord 74ac86 vdd e20 gnd e21 e19 r42 100 xorc drb r45 00 11 u9 74ac86 12 13 dcoca xorc vdd gnd c32 0.1 f dcot dcota r16 00 dcoc dcoca r17 00 figure 13b. pcb schematic (continued)
rev. 0 ad9410 C17C troubleshooting if the board does not seem to be working correctly, try the following: verify power at ic pins. check that all jumpers are in the correct position for the desired mode of operation. verify vref is at 2.5 v. try running encode clock and analog input at low speeds ( 10 msps/1 mhz ) and monitor latch outputs, dac outputs, and adc outputs for toggling. the ad9410 evaluation board is provided as a design example for customers of analog devices, inc. adi makes no warranties, express, statutory, or implied, regarding merchantability or fitness for a particular purpose. ad9751 u2 e34 gnd e33 dcoca dcota gnd c13 0.1 f gnd dm9 dm8 dm7 dm6 dm5 dm4 e35 dn0 dn1 dn2 dn3 dn4 dn5 dn6 dn7 dn8 dn9 gnd c17 0.1 f gnd vdac dm0 dm1 dm2 dm3 e29 e31 vdac e30 gnd e2 vdac e5 gnd e4 c23 0.1 f gnd r10 2k gnd c3 0.1 f vdac gnd c20 0.1 f r13 392 gnd gnd r12 50 gnd r1 50 gnd j4 1 2 3 4 5 6 7 8 9 11 12 10 13 14 15 16 17 18 19 20 21 23 24 22 36 35 34 33 32 31 30 29 28 26 25 27 48 47 46 45 44 43 42 41 40 38 37 39 vdac r5 392 gnd gnd vdac vdac c33 1 f vdac e32 j3 gnd figure 13c. pcb schematic (continued)
rev. 0 ad9410 C18C figure 14. top silkscreen figure 15. split power plane figure 16. ground plane evaluation board layout figure 17. bottom components and routing figure 18. bottom silkscreen figure 19. top components and routing
rev. 0 ad9410 C19C ad9410 evaluation board bill of material quantity reference description device package value 5c1 c5 capacitor tajd 10 f 29 c6 c30, c32, c37, c39, c40 capacitor 603 0.1 f 1 c33 capacitor 1206 1 f 31 e1 e7, e10 e12, e14, e16 e35 ehole 6 j1, j3, j4, j8, j9x, j10x smb 3 p1, p4, p5 4-pin power 25.531.3425.0 wieland connector 25.602.5453.0 2 p2, p3 40-pin header 7 r1, r8, r12, r23 * , r25x, r26, r27 resistor 1206 50 ? 8 r2, r3, r4, r6, r24, r37, r42, r43 resistor 1206 100 ? 1 r13 resistor 1206 392 ? 1 r7 resistor 1206 100 ? 2 r9, r18 resistor 1206 24 k ? 1 r10 resistor 1206 2 k ? 2 r11, r15 resistor 1206 330 ? 2 r14, r19 resistor 1206 8.2 k ? 5 r5, r16, r17, r44, r45 resistor 1206 0 ? 8 r28, r29, r32, r34, r36, r38 r40 rpack 766163220g cts 22 ? 1 t1 transformer (1:1) adt1-1wt minicircuits 1 u1 mc10el16 soic8 1 u2 ad9751 lqfp48 1 u3 ad9410 lqfp80 2 u4, u5 74lcx821 soic24 1 u9 74ac86 soic14 * optional r23 not placed on board (50 ? termination resistor).
rev. 0 C20C c01679C4.5C10/00 (rev. 0) printed in u.s.a. ad9410 outline dimensions dimensions shown in inches and (mm). 80-lead powerquad 2 (lqfp_ed) (sq-80) 1 20 21 41 40 60 80 61 pin 1 top view (pins down) 0.630 (16.00) sq 0.551 (14.00) sq seating plane 0.063 (1.60) max 0.004 (0.10) max coplanarity 0.006 (0.15) 0.002 (0.05) 0.030 (0.75) 0.024 (0.60) 0.018 (0.45) 0.0256 (0.65) bsc 7 0 0.008 (0.20) 0.004 (0.09) 0.015 (0.38) 0.013 (0.32) 0.009 (0.22) 0.057 (1.45) 0.055 (1.40) 0.053 (1.35) controlling dimension in millimeters. center figures are typical unless otherwise noted. 1 20 21 41 40 60 80 61 xx bottom view nickel plated 0.120 (3.04) 45 c chamfer 4 places 0.413 (10.50) 0.394 (10.00) ref 0.374 (9.50) 0.413 (10.50) 0.394 (10.00) ref 0.374 (9.50) note the ad9410 has a conductive heat slug to help dissipate heat and ensure reliable operation of the device over the full indus- trial temperature range. the slug is exposed on the bottom of the package. it is recommended that no pcb traces or vias be located under the package that could come in contact with the conductive slug. attaching the slug to a ground plane while not required in most applications will reduce the junction tempera- ture of the device which may be beneficial in high temperature environments.

▲Up To Search▲

Price & Availability of AD9410BSQ

	To Download AD9410BSQ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .